/home/cpan/workspace/llvm-project-dev/llvm-project/llvm/include/llvm/CodeGen/ScheduleDAG.h class ScheduleDAG { public: const LLVMTargetMachine &TM; ///< Target processor const TargetInstrInfo *TII; ///< Target instruction information const TargetRegisterInfo *TRI; ///< Target processor register info MachineFunction &MF; ///< Machine function MachineRegisterInfo &MRI; ///< Virtual/real register map std::vector SUnits; ///< The scheduling units. SUnit EntrySU; ///< Special node for the region entry. SUnit ExitSU; ///< Special node for the region exit.
/home/cpan/workspace/llvm-project-dev/llvm-project/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h /// A ScheduleDAG for scheduling lists of MachineInstr. class ScheduleDAGInstrs : public ScheduleDAG
-mllvm -debug -mllvm -print-after-all
*** IR Dump After Scalarize Masked Memory Intrinsics *** ScalarizeMaskedMemIntrin.cpp This pass replaces masked memory intrinsics - when unsupported by the target with a chain of basic blocks, that deal with the elements one-by-one if the appropriate mask bit is set.
*** IR Dump After Module Verifier *** define void @main(i8* %addr_dout, i32 %din0, i32 %din1) { %res0 = call i32 @llvm.dtu.abs.a(i32 %din0) call void @llvm.dtu.st.w.p0i8(i32 %res0, i8* %addr_dout, i32 0) %res1 = call i32 @llvm.dtu.abs.t(i32 %din0, i32 %res0) call void @llvm.dtu.st.w.p0i8(i32 %res1, i8* %addr_dout, i32 0) %res2 = call i32 @llvm.dtu.abs.f(i32 %din0, i32 %res0) call void @llvm.dtu.st.w.p0i8(i32 %res2, i8* %addr_dout, i32 0) %res3 = call i32 @llvm.dtu.abs.c(i32 %din0, i32 %res0) call void @llvm.dtu.st.w.p0i8(i32 %res3, i8* %addr_dout, i32 0) ret void }
https://llvm.org/docs/CodeGenerator.html#target-independent-code-generation-algorithms
Introduction to SelectionDAGs The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the SDNode class.
SelectionDAGs contain two different kinds of values: those that represent data flow and those that represent control flow dependencies.
Data values are simple edges with an integer or floating point value type. Control edges are represented as “chain” edges which are of type MVT::Other.
after instruction selection, the machine nodes have their chain after the instruction’s operands, and may be followed by glue nodes.
A SelectionDAG has designated “Entry” and “Root” nodes. The Entry node is always a marker node with an Opcode of ISD::EntryToken. The Root node is the final side-effecting node in the token chain.
One important concept for SelectionDAGs is the notion of a “legal” vs. “illegal” DAG. A legal DAG for a target is one that only uses supported operations and supported types.
SelectionDAG Instruction Selection Process 1.Build initial DAG 2.Optimize SelectionDAG 3.Legalize SelectionDAG Types 4.Optimize SelectionDAG 5.Legalize SelectionDAG Ops 6.Optimize SelectionDAG 7.Select instructions from DAG:This process translates the target-independent input DAG into another DAG of target instructions. 8.SelectionDAG Scheduling and Formation
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