aarch32? ?armv7? ?linux 4.9
经常书中会写到上下文切换的tlb flush的时候为了减少开销，tlb 会有延迟刷新? lru 替换策略
这个具体的问题，内核怎样配合ip core的实现的呢
1.A?translation lookaside buffer?(TLB) is a memory?cache?that is used to reduce the time taken to access a user memory location.?It is a part of the chip's?memory-management unit?(MMU). The TLB stores the recent translations of?virtual memory?to?physical memory?and can be called an address-translation cache. A TLB may reside between the?CPU?and the?CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache.?
------------from维基百科
2.cache 与tlb
cache speed up cpu access，tlb speed up vaddr translattion
tlb存储的是page table item，cache 存储的是data或者instruction
两者都有可能有L1L2多级，也可能都有data cache/tlb，instruction cache/tlb
3.ASID address space id
进程上下文切换的时候，内存映射不一样，tlb需要flush重新映射，ASID是为了应对这种开销诞生的策略之一，每个进程有唯一的ASID，进程切换的时候就不需要再去flush tlb了
4. global属性
tlb global 和local 两种属性?内核的页表tlb项为global类型，可以一直驻留在tlb里面
In a VMSA implementation, system software can divide a virtual memory map used by memory accesses at PL1 and PL0 into global and non-global regions, indicated by the nG bit in the translation table descriptors:
nG == 0
The translation is global, meaning the region is available for all processes.
nG == 1
The translation is non-global, or process-specific, meaning it relates to the current ASID, as defined by the?CONTEXTIDR.
Each non-global region has an associated?Address Space Identifier?(ASID). These identifiers mean different translation table mappings can co-exist in a caching structure such as a TLB. This means that software can create a new mapping of a non-global memory region without removing previous mappings.