[嵌入式]STM32F030 串口uart1接收字节数据最高位1置1问题

STM32F030c8 使用串口uart1串口2uart2的时候,发现中断接收数据的时候每个字节都会最高位置1

?最终发现使用内部晶振HSI问题导致[注意是同时使用PF0 PF1,错误关闭HSE].RCC初始化配置错误,导致这个奇怪问题,最终找了一个正确的HSI初始化RCC程序,问题解决,

void SetSysClock(void)
{
  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  
  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/

 
	//Enable HSI
	RCC->CR |= RCC_CR_HSION;
	//Wait till Hsi is ready	
	do
  {
   HSIStatus = RCC->CR & RCC_CR_HSIRDY;
    StartUpCounter++;  
  } while((HSIStatus== 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
	 if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
  {
		HSIStatus = (uint32_t)0x01;
  }
  else  
  {
		HSIStatus = (uint32_t)0x00;
  }  
	if(HSIStatus==(uint32_t)0x01)
	{
		/* Enable Prefetch Buffer and set Flash Latency */
		FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
				//Set AHB prescaler /1  48M
		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
		//Set APB prescaler /1 48M
		RCC->CFGR |= RCC_CFGR_PPRE_DIV1;
		
		 /* PLL configuration = HSI/2 * 12= 48 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
		
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12); //RC时钟2分频后 进行12倍频</font>
		
		
//		//Select Pllsrc as hsi already reset & pllmul *12  8/2*12=48M
//		RCC->CFGR |= RCC_CFGR_PLLMUL12;
		
		/* Enable PLL */
		RCC->CR |= RCC_CR_PLLON;
		/* Wait till PLL is ready */
		while((RCC->CR & RCC_CR_PLLRDY) == 0);
		
		//select system clock as pll
		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
		RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
		
		//wait pll use as system clock
		while((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL);
 
		//Set ADC prescaler /4  12M
	//	RCC->CFGR |= RCC_ADCCLK_PCLK_Div4;
		//Set ADC clock source
		RCC_ADCCLKConfig(RCC_ADCCLK_PCLK_Div4);
		//Set usart clock source
		RCC_USARTCLKConfig(RCC_USART1CLK_PCLK);
		//Set IIC clock source
		RCC_I2CCLKConfig(RCC_I2C1CLK_SYSCLK);	
		
  }

}